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User’s Guide, EVD1000 Developer’s Kit – Analog
User-customizable Presets
The EVD application also includes a mechanism whereby parameter settings as defined on the slider
panel may be stored into the three presets on the Demonstrator board, for later use with the board in
stand-alone mode (without USB connection). This allows a customer to configure the board with
enhancement capability of their own choosing, tailored for a specific application, and then, for
example, send it out for operation in the field in compact form without the need for additional ancillary
equipment. The customizable preset capability on the Demonstrator boards can also be accessed
directly via the USB interface. The use of these features is also described in detail in an additional
Application Note.
Circuit Implementation
The block diagram below is representative of the Demonstrator board, and also provides a simple
example application for use in an existing analog camera chain, e.g. as an add-on for a security video
system. It shows all of the possible major commonly used inputs/outputs of the EVD1000, but
highlights the very simple basic connections required for operation in this mode.
+3.3V
+1.8V
SD VIDEO DECODER
VCC_BUF
EVD1000
VCC_CORE
SD VIDEO ENCODER
(128 pin TQFP)
Composite video input
CVBS_IN
BT656_DATA[9:0]
G_Y_IN[9:0]
G_Y_OUT[9:0]
BT656_DATA[9:0]
CVBS_OUT
Composite video output
R_CR_IN[9:0]
R_CR_OUT[9:0]
Y_IN
B_CB_CRCB_IN[9:0]
B_CB_CRCB_OUT[9:0]
Y_OUT
S-video video input
C_IN
HBLNK_IN, VBLNK_IN
HSYNC_IN, VSYNC_IN
FIELD_IN
HBLNK_OUT, VBLNK_OUT
HSYNC_OUT, VSYNC_OUT
FIELD_OUT
C_OUT
S-video video output
SCL, SDA
2xPIX_CLK
27 MHz
SCL, SDA
2xPIX_CLK
SCL, SDA
CLK_VIDEO
CLK_SYSTEM
VSS
MICROCONTROLLER
GND
User interface
USER INTERFACE
SCL, SDA
Here, video input and output for the EVD1000 is shown as ITU-R BT.656 digital data with embedded
SAV and EAV codes (hence the use of blanking/sync inputs/outputs are not required). The standard
video decoder and encoder handle the conversion to/from analog video signals which are in this case
external to the board. Note that in this mode, the video data clock for all components on the board
(as derived from the analog sync information by the video decoder) runs at 27 MHz (twice the pixel
rate), as luminance and chrominance values alternate in the digital data stream for Bt656 format. As
can be seen from the diagram, this is a particularly simple and easy-to-implement connection
? 2009 Enhanced Video Devices, Inc. DKA-SC Rev 1.1 5/25/2009
Page 5
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